Paul Goedeke is an applications engineer at Texas Instruments. If there is a potential issue, reduce the values of the feedback network resistances, or consider using a compensation capacitor. Take the extra time to verify that the input capacitances will not impact stability. Input capacitance is particularly a concern when using high GBW op amps and large feedback resistors. Often overlooked op-amp parameters such as input capacitance may cause stability issues. After compensating with CF, the phase margin is increased to 86 degrees.įigure 14 Stability with a compensation capacitor The stability analysis for the uncompensated circuit yields a phase margin of 10 degrees. For more information on simulating op-amp parameters, see the series, “ Designing with a complete simulation test bench for op amps.” įigure 14 compares the uncompensated circuit to the compensated version and shows that the capacitor stabilizes the circuit well. If a SPICE model doesn’t include this capacitance, add a capacitor to the op-amp inverting input, similar to what is shown in Figure 10. Newer op-amp models from TI accurately model input capacitance and open-loop gain, which are necessary for accurate stability simulations. For a robust design, it is best to be conservative when choosing C F because of component tolerances and device input capacitance variations. You can fine-tune the placement of f z_cf by starting with the results of Equation 12 and then simulating. If you need to maximize the overall bandwidth of the circuit, f z_cf can be greater than f p_cin but less than BW CL. The new closed-loop bandwidth with a compensation capacitor is equal to the zero frequency created by C F and R2. This method of compensation reduces the system bandwidth. Again following the recommendation of making f p_cin between 2 and 10 times larger than BW CL, Equation 10 provides a range of GBW:įigure 10 Using a compensation capacitor, C FĮquation 11 sets the pole and zero frequencies equal to each other to ensure that the zero corner frequency is inside the closed-loop bandwidth:Įquation 12 calculates the capacitance needed to stabilize the system: You can also rearrange Equation 5 to find the highest acceptable GBW op amp for a given R eq. Įquations 7 and 8 will help choose the magnitudes of the feedback resistors:įor the inverting circuit, Equation 9 determines R2 as: Solve for R1 and R2 so that f p_cin is between 2 and 10 times larger than BW CL. For a noninverting circuit, use Equation 2 as the constraint for the ratio of R1 and R2 and then rearrange Equation 5. Therefore, it is best to make f p_cin between 2 and 10 times larger than BW CL. If f p_cin is only slightly more than BW CL, it will still impact the loop gain phase margin. As long as BW CL is a lower frequency than the pole frequency determined by the right-hand side of the equation, there will be minimal impact on system stability from the input capacitance.Ī pole or zero starts to impact the phase of a system one decade before the corner frequency. The left-hand side of Equation 6 defines the closed-loop bandwidth, BW CL. Where G cl is the noninverting closed-loop gain of the system as shown in Equation 2 and GBW is the gain bandwidth of the op amp. While you don’t usually use extreme resistor values (tens of ohms or gigaohms) because of op-amp input bias current and output current limits, kiloohm-value resistors may cause issues by interacting with an op amp’s input capacitance.Įquation 6 makes it easy to check if there is a potential issue: One is to consider the input capacitance when choosing the magnitude of resistors for the circuit’s feedback network. Now that you understand the impact of input capacitance, there are a few ways to address the problem.
Using Equation 5, the higher gain circuit will have a pole frequency nearly five times greater than the lower gain circuit.įinishing the design and making it stable For example, compare the equivalent resistance at two different gains: Looking at Equations 1 and 2, it’s possible to obtain higher gains with smaller values of R1. One additional advantage of a higher gain configuration is a typically lower equivalent resistance for the feedback network. Figure 9 ROC with increased closed-loop gain
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